Newmorphic · Established 2026

One transistor.
One neuron.

N-01 · 300 MM · CMOS 10⁶ NEURONS · STANDARD FLOW 50 mm

We built the world's first single-transistor neuron and synapse. Drop-in compatible with any CMOS foundry. No exotic materials. No new fabs. Just standard silicon, engineered to think.

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01The Problem

The architecture under modern AI is broken.

Every chip running every AI system today was designed for one job — switch on, switch off. The mismatch between that design and the work we now ask it to do is the central engineering problem of this decade.

01
Computation and memory, separated.
Every calculation in every chip moves data between two physically distinct places. At AI scale, that movement is where almost all the energy goes. The bottleneck is architectural, not technological.
02
Density without architecture.
Forty years of process scaling has made the transistor smaller. The architecture it serves has not meaningfully changed since 1947.
03
The materials cul-de-sac.
Every attempt to escape this through new memory materials — memristors, phase-change, exotic stacks — has stalled at the same place. Yield collapses, drift accumulates, the factory bar holds. Forty years of effort, no platform.
02The Answer

A single transistor. A complete neuron.

One device. Memory and compute in the same place. Standard CMOS, no new materials. The three problems collapse into a single primitive.

Conventional silicon treats switching as binary. We discovered a regime where the same MOSFET, the building block of every chip ever shipped, produces spiking dynamics identical to a biological neuron.

The physics: sub-threshold integration, leaky firing, refractory recovery. All of it, from one device. No capacitors, no resistive memory, no memristive stack.

The implication: neuromorphic computing is no longer a materials problem. It's an architecture problem. And it's solvable, today, at any foundry.

DEVICE · CROSS-SECTION 130 nm P-SUB S D G SPIKING OUTPUT · f(V_tune, I_in) 0.46 μm
03How it Works

Three principles. One device.

Every aspect of the technology is designed to collapse what neuromorphic hardware typically takes dozens of components to achieve and into the footprint of a standard MOSFET.

Dynamics

Spiking behaviour, intrinsic.

Sub-threshold integration plus leak plus refractory recovery: the full LIF (leaky integrate-and-fire) dynamic, produced by the MOSFET's own physics. No external capacitor. No RC network. The neuron is the transistor.

Manufacturability

Drops into any foundry.

No exotic oxides. No memristive materials. No 3-D stacking requirements. The device is fabricated in a standard CMOS process. 130 nm, FinFET, nano-ribbon, CFET. If a foundry can run logic, it can run us.

Integration

Designer-ready on day one.

Full SPICE model across the operational tuning space. Chip designers simulate and place Newmorphic cells using the same flow they already use for every other block: Cadence, Synopsys, industry-standard EDA. No new workflow.

04Proven in Silicon

Engineered. Measured. Real.

Q1 2026 · 3-wafer pilot · 130 nm CMOS
Fully-integrated, silicon-validated device data in characterised chips. Every result below is measured, not simulated. The roadmap for wafer-level validation is underway.
7pJ
Firing Energy · min
Per neuron firing event on a 0.46 μm device. 60× lower than our 2025 result; competitive with purpose-built neuromorphic cores.
1B+
Neuron Cycles
Endurance in 130 nm MOSFETs under fast ramp cycling, with a firing window maintained at >100×.
100%
Device Yield
Every device works. Ultra-low device-to-device variability across the pilot lot, with wafer-level validation in progress.
SPICEready
Design-Ready
Neuron electrical behaviour modelled in foundry-standard SPICE across the full operational tuning space.
05Reliability

Reliability that survives a foundry.

The endurance plot every other neuromorphic platform fails. Same axes, same scale, side by side. Across nine decades of cycles.

The Incumbent
Memristors
50%
Devices that work
HRS / LRS · Cycle endurance
HRS LRS 100102104106108 CYCLES AT 10⁵ CYCLES closed MEMORY WINDOW
Newmorphic · Standard CMOS
NS-RAM
100%
Devices that work
HRS / LRS · Cycle endurance
HRS LRS 100102104106108 >100× WINDOW CYCLES AT 10⁵ CYCLES 100× NS-RAM WINDOW
Validated in 130 nm CMOS
3-wafer pilot · 100% yield
06Where it Goes

Applications across the stack.

The same device, in many shapes. The substrate is general-purpose; this is where it begins.

01 / Audio & Voice

Always-on, micro-watt.

Tonotopic wake-word, speaker ID, and in-ear noise cancellation running below the noise floor of today's DSPs.

02 / Autonomous Systems

Real-time event vision.

Event-based sensing for drones, robotics and vehicles. Latency-first inference with biological efficiency.

03 / Medical & Wearables

On-body inference, always.

Continuous biosignal analysis: ECG, EEG, EMG. On devices that run for weeks on a single coin cell.

04 / IoT & Sensor Fusion

Intelligent at the source.

Decision-ready telemetry from distributed sensor meshes. No backhaul, no cloud dependency.

05 / Space & Defence

Rad-hardened by design.

Standard CMOS heritage means mature rad-hard process compatibility for on-orbit and tactical edge.

06 / Autonomous Systems

Microsecond latency.

Real-time control for robotics, vehicles and drones. Decisions made on the device, at the speed the device needs them.

07Company

A foundry-native approach to neuromorphic.

We believe the next decade of AI hardware will be decided not by who invents the best new material, but by who can deliver the most efficient compute through the fab lines that already exist.

Mario Lanza
Co-Founder · Chief Scientist
Assoc. Professor, NUS. IEEE Fellow. Former Stanford, KAUST, Peking University. Board of Governors, IEEE Electron Devices Society. 200+ publications.
Sebastian Pazos
Co-Founder · CTO
Research Scientist, NUS. Lead inventor of NS-RAM. Co-author, Nature 2025. Deep expertise in CMOS device physics, TCAD simulation, and circuit design.
David Pevcic
Co-Founder · Chairman
Experienced executive and investor in resources & technology sectors. Chairman of Nanoveu Ltd (ASX:NVU), Battery Age Minerals Ltd (ASX: BM8) and Infini Resources Ltd (ASX: I88). BSc, MBBS.
Alfred Chong
Co-Founder · CEO
30+ years scaling companies and trade sales. Former CEO of Atex Media Command (APAC), THISS Technologies. Founder, Nanoveu.
08The Explainer

What was found inside the transistor.

09Insights

Writing from the lab.

Technical deep-dives, silicon measurements, and field notes from building the first foundry-native neuromorphic primitives.

Device Physics · Coming Soon
Why sub-threshold MOSFETs behave like neurons, and what took us so long to notice.
Silicon Notes · Coming Soon
Inside the Q1 2026 pilot: 60× energy reduction, what we learned from the yield data.
Field · Coming Soon
The foundry-native thesis: why new materials keep losing to new ideas on old silicon.
10Contact

Let's talk.

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